library verilog;
use verilog.vl_types.all;
entity cmsdk_ahb_slave_mux is
    generic(
        PORT0_ENABLE    : integer := 1;
        PORT1_ENABLE    : integer := 1;
        PORT2_ENABLE    : integer := 1;
        PORT3_ENABLE    : integer := 1;
        PORT4_ENABLE    : integer := 1;
        PORT5_ENABLE    : integer := 1;
        PORT6_ENABLE    : integer := 1;
        PORT7_ENABLE    : integer := 1;
        PORT8_ENABLE    : integer := 1;
        PORT9_ENABLE    : integer := 1;
        PORT10_ENABLE   : integer := 1;
        DW              : integer := 32
    );
    port(
        HCLK            : in     vl_logic;
        HRESETn         : in     vl_logic;
        HREADY          : in     vl_logic;
        HSEL0           : in     vl_logic;
        HREADYOUT0      : in     vl_logic;
        HRESP0          : in     vl_logic;
        HRDATA0         : in     vl_logic_vector;
        HSEL1           : in     vl_logic;
        HREADYOUT1      : in     vl_logic;
        HRESP1          : in     vl_logic;
        HRDATA1         : in     vl_logic_vector;
        HSEL2           : in     vl_logic;
        HREADYOUT2      : in     vl_logic;
        HRESP2          : in     vl_logic;
        HRDATA2         : in     vl_logic_vector;
        HSEL3           : in     vl_logic;
        HREADYOUT3      : in     vl_logic;
        HRESP3          : in     vl_logic;
        HRDATA3         : in     vl_logic_vector;
        HSEL4           : in     vl_logic;
        HREADYOUT4      : in     vl_logic;
        HRESP4          : in     vl_logic;
        HRDATA4         : in     vl_logic_vector;
        HSEL5           : in     vl_logic;
        HREADYOUT5      : in     vl_logic;
        HRESP5          : in     vl_logic;
        HRDATA5         : in     vl_logic_vector;
        HSEL6           : in     vl_logic;
        HREADYOUT6      : in     vl_logic;
        HRESP6          : in     vl_logic;
        HRDATA6         : in     vl_logic_vector;
        HSEL7           : in     vl_logic;
        HREADYOUT7      : in     vl_logic;
        HRESP7          : in     vl_logic;
        HRDATA7         : in     vl_logic_vector;
        HSEL8           : in     vl_logic;
        HREADYOUT8      : in     vl_logic;
        HRESP8          : in     vl_logic;
        HRDATA8         : in     vl_logic_vector;
        HSEL9           : in     vl_logic;
        HREADYOUT9      : in     vl_logic;
        HRESP9          : in     vl_logic;
        HRDATA9         : in     vl_logic_vector;
        HREADYOUT       : out    vl_logic;
        HRESP           : out    vl_logic;
        HRDATA          : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of PORT0_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT1_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT2_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT3_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT4_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT5_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT6_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT7_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT8_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT9_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of PORT10_ENABLE : constant is 1;
    attribute mti_svvh_generic_type of DW : constant is 1;
end cmsdk_ahb_slave_mux;
